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19-0377; Rev 1; 12/97
KIT ATION EVALU LE B AVAILA
16-Bit, 85ksps ADC with 10A Shutdown
_______________General Description
The MAX195 is a 16-bit successive-approximation analog-to-digital converter (ADC) that combines high speed, high accuracy, low power consumption, and a 10A shutdown mode. Internal calibration circuitry corrects linearity and offset errors to maintain the full rated performance over the operating temperature range without external adjustments. The capacitive-DAC architecture provides an inherent 85ksps track/hold function. The MAX195, with an external reference (up to +5V), offers a unipolar (0V to VREF) or bipolar (-VREF to VREF) pin-selectable input range. Separate analog and digital supplies minimize digital-noise coupling. The chip select (CS) input controls the three-state serialdata output. The output can be read either during conversion as the bits are determined, or following conversion at up to 5Mbps using the serial clock (SCLK). The end-ofconversion (EOC) output can be used to interrupt a processor, or can be connected directly to the convert input (CONV) for continuous, full-speed conversions. The MAX195 is available in 16-pin DIP, wide SO, and ceramic sidebraze packages.
____________________________Features
o 16 Bits, No Missing Codes o 90dB SINAD o 9.4s Conversion Time o o o o 10A (max) Shutdown Mode Built-In Track/Hold AC and DC Specified Unipolar (0V to VREF) and Bipolar (-VREF to VREF) Input Range o Three-State Serial-Data Output o Small 16-Pin DIP, SO, and Ceramic SB Packages
MAX195
______________Ordering Information
PART MAX195BCPE MAX195BCWE MAX195ACDE MAX195BC/D MAX195BEPE MAX195BEWE MAX195AEDE MAX195AMDE MAX195BMDE TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C PIN-PACKAGE 16 Plastic DIP 16 Wide SO 16 Ceramic SB Dice* 16 Plastic DIP 16 Wide SO 16 Ceramic SB 16 Ceramic SB** 16 Ceramic SB**
________________________Applications
Portable Instruments Audio Industrial Controls Robotics Multiple Transducer Measurements Medical Signal Acquisition Vibrations Analysis Digital Signal Processing
* Dice are specified at TA = +25C, DC parameters only. ** Contact factory for availability and processing to MIL-STD-883.
________________Functional Diagram
13 12 MAIN DAC
__________________Pin Configuration
TOP VIEW
BP/UP/SHDN 1 CLK 2 SCLK 3 VDDD 4 DOUT 5 DGND 6 EOC 7 CS 8 16 VDDA 15 VSSA 14 AGND
AIN REF
CALIBRATION DACs SAR 2 CLK SCLK CONV BP/UP/SHDN CS RESET 3 9 1 8 10 CONTROL LOGIC
COMPARATOR
4 6 11 16 14 15
VDDD DGND VSSD VDDA AGND VSSA
MAX195
13 AIN 12 REF 11 VSSD 10 RESET 9 CONV
MAX195
5 THREE-STATE BUFFER 7 EOC DOUT
DIP/Wide SO/Ceramic SB ________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468.
16-Bit, 85ksps ADC with 10A Shutdown MAX195
ABSOLUTE MAXIMUM RATINGS
VDDD to DGND .....................................................................+7V VDDA to AGND......................................................................+7V VSSD to DGND.........................................................+0.3V to -6V VSSA to AGND .........................................................+0.3V to -6V VDDD to VDDA, VSSD to VSSA ..........................................0.3V AIN, REF ....................................(VSSA - 0.3V) to (VDDA + 0.3V) AGND to DGND ..................................................................0.3V Digital Inputs to DGND...............................-0.3V, (VDDA + 0.3V) Digital Outputs to DGND............................-0.3V, (VDDA + 0.3V) Continuous Power Dissipation (TA = +70C) Plastic DIP (derate 10.53mW/C above +70C) ............842mW Wide SO (derate 9.52mW/C above +70C)..................762mW Ceramic SB (derate 10.53mW/C above +70C)...........842mW Operating Temperature Ranges MAX195_C_E ........................................................0C to +70C MAX195_E_E .....................................................-40C to +85C MAX195_MDE..................................................-55C to +125C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, fCLK = 1.7MHz, VREF = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER ACCURACY (Note 1) Resolution Differential Nonlinearity Integral Nonlinearity Unipolar/Bipolar Offset Error Unipolar/Bipolar Offset Tempco Unipolar Full-Scale Error Bipolar Full-Scale Error Full-Scale Tempco Power-Supply Rejection Ratio (VDDA and VSSA only) ANALOG INPUT Input Range Input Capacitance Unipolar Bipolar Unipolar Bipolar 0 -VREF 250 125 VREF VREF V pF VDDA = 4.75V to 5.25V, VREF = 4.75V VSSA = -5.25V to -4.75V, VREF = 4.75V 65 65 VREF = 4.75V VREF = 4.75V 0.1 RES DNL INL MAX195A MAX195B MAX195A MAX195B MAX195A, VREF = 4.75V MAX195B, VREF = 4.75V 0.4 0.0075 0.018 16 1 2 0.003 0.004 3 4 Bits LSB %FSR LSB ppm/C %FSR %FSR ppm/C dB SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC PERFORMANCE (fs = 85kHz, bipolar range AIN = -5V to +5V, 1kHz) (Note 1) Signal-to-Noise plus Distortion Ratio (Note 2) Total Harmonic Distortion (up to the 5th harmonic) (Note 2) Peak Spurious Noise (Note 2) Conversion Time Clock Frequency (Notes 3, 4) Serial Clock Frequency tCONV fCLK fSCLK SINAD THD TA = +25C TA = +25C TA = +25C 16 (tCLK) 9.4 1.7 5 87 90 -97 -90 -90 dB dB dB s MHz MHz
2
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16-Bit, 85ksps ADC with 10A Shutdown
ELECTRICAL CHARACTERISTICS (continued)
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, fCLK = 1.7MHz, VREF = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER CLK, CS, CONV, RESET, SCLK Input High Voltage CLK, CS, CONV, RESET, SCLK Input Low Voltage CLK, CS, CONV, RESET, SCLK Input Capacitance (Note 3) CLK, CS, CONV, RESET, SCLK Input Current BP/UP/SHDN Input High Voltage BP/UP/SHDN Input Low Voltage BP/UP/SHDN Input Current, High BP/UP/SHDN Input Current, Low BP/UP/SHDN Mid Input Voltage BP/UP/SHDN Voltage, Floating BP/UP/SHDN Max Allowed Leakage, Mid Input DIGITAL OUTPUTS (DOUT, EOC) Output Low Voltage Output High Voltage DOUT Leakage Current Output Capacitance (Note 2) POWER REQUIREMENTS VDDD VSSD VDDA VSSA VDDD Supply Current VSSD Supply Current VDDA Supply Current VSSA Supply Current IDDD ISSD IDDA ISSA By supply-rejection test By supply-rejection test VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V 4.75 -5.25 4.75 -5.25 2.5 0.9 3.8 3.8 5.25 -4.75 5.25 -4.75 4 2 5 5 V V V V mA mA mA mA VOL VOH ILKG VDDD = 4.75V, ISINK = 1.6mA VDDD = 4.75V, ISOURCE = 1mA DOUT = 0 or 5V VDDD - 0.5 10 10 0.4 V V A pF VIH VIL IIH IIL VIM VFLT BP/UP/SHDN = open BP/UP/SHDN = open -100 BP/UP/SHDN = VDDD BP/UP/SHDN = 0V -4.0 1.5 VDDD - 1.5 2.75 +100 Digital inputs = 0 or 5V VDDD - 0.5 0.5 4.0 SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (CLK, CS, CONV, RESET, SCLK, BP/UP/SHDN) VIH VIL VDDD = 5.25V VDDD = 4.75V 2.4 0.8 10 10 V V pF A V V A A V V nA
MAX195
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16-Bit, 85ksps ADC with 10A Shutdown MAX195
ELECTRICAL CHARACTERISTICS (continued)
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, fCLK = 1.7MHz, VREF = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Power Dissipation VDDD Shutdown Supply Current (Note 5) VSSD Shutdown Supply Current VDDA Shutdown Supply Current VSSA Shutdown Supply Current Note 1: Note 2: Note 3: Note 4: Note 5: IDDD ISSD IDDA ISSA SYMBOL CONDITIONS VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V, BP/UP/SHDN = 0V VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V, BP/UP/SHDN = 0V VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V, BP/UP/SHDN = 0V VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V, BP/UP/SHDN = 0V 1.6 0.1 0.1 0.1 MIN TYP MAX 80 5 5 5 5 UNITS mW A A A A POWER REQUIREMENTS (cont.)
Accuracy and dynamic performance tests performed after calibration. Guaranteed by design, not tested. Tested with 50% duty cycle. Duty cycles from 25% to 75% at 1.7MHz are acceptable. See External Clock section. Measured in shutdown mode with CLK and SCLK low.
TIMING CHARACTERISTICS
(VDDD = VDDA = +5V, VSSD = VSSA = -5V, unless otherwise noted.) PARAMETER CONV Pulse Width CONV to CLK Falling Synchronization (Note 2) CONV to CLK Rising Synchronization (Note 2) Data Access Time Bus Relinquish Time CLK to EOC High CLK to EOC Low CLK to DOUT Valid SCLK to DOUT Valid CS to SCLK Setup Time CS to SCLK Hold Time Acquisition Time Calibration Time RESET to CLK Setup Time RESET to CLK Hold Time Start-Up Time (Note 6) SYMBOL CONDITIONS tCW tCC1 tCC2 tDV tDH tCEH tCEL tCD tSD tCSS tCSH tAQ tCAL tRCS tRCH tSU Exiting shutdown 50 14,000 x tCLK CL = 50pF CL = 10pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF 100 20 75 -10 2.4 8.2 -40 120 TA = +25C TYP TA = 0C to +70C MIN MAX 20 10 40 80 40 300 300 350 140 100 20 75 -10 2.4 8.2 -40 120 TA = -40C to +85C MIN MAX 30 10 40 80 40 300 300 375 160 100 20 75 -10 2.4 8.2 -40 120 TA = -55C to +125C MIN MAX 35 10 40 90 40 350 350 400 160 UNITS ns ns ns ns ns ns ns ns ns ns ns s ms ns ns s
Note 6: Settling time required after deasserting shutdown to achieve less than 0.1LSB additional error.
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16-Bit, 85ksps ADC with 10A Shutdown
______________________________________________________________Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME BP/UP/SHDN CLK SCLK VDDD DOUT DGND EOC CS CONV RESET VSSD REF AIN AGND VSSA VDDA FUNCTION Bipolar/Unipolar/Shutdown Input. Three-state input selects bipolar or unipolar input range, or shutdown. 0V = shutdown, +5V = unipolar, floating = bipolar. Conversion Clock Input Serial Clock Input is used to shift data out between conversions. May be asynchronous to CLK. +5V Digital Power Supply Serial Data Output, MSB first Digital Ground End-of-Conversion/Calibration Output--normally low. Rises one clock cycle after the beginning of conversion or calibration and falls one clock cycle after the end of either. May be used as an output framing signal. Chip-Select Input--active low. Enables the serial interface and the three-state data output (DOUT). Convert-Start Input--active low. Conversion begins on the falling edge after CONV goes low if the input signal has been acquired; otherwise, on the falling clock edge after acquisition. Reset Input. Pulling RESET low places the ADC in an inactive state. Rising edge resets control logic and begins calibration. -5V Digital Power Supply Reference Input, 0 to 5V Analog Input, 0 to VREF unipolar or VREF bipolar range Analog Ground -5V Analog Power Supply +5V Analog Power Supply
MAX195
_______________Detailed Description
The MAX195 uses a successive-approximation register (SAR) to convert an analog input to a 16-bit digital code, which outputs as a serial data stream. The data bits can be read either during the conversion, at the CLK clock rate, or between conversions asynchronous with CLK at the SCLK rate (up to 5Mbps). The MAX195 includes a capacitive digital-to-analog converter (DAC) that provides an inherent track/hold input. The interface and control logic are designed for easy connection to most microprocessors (Ps), limiting the need for external components. In addition to the SAR and DAC, the MAX195 includes a serial interface, a sampling comparator used by the SAR, ten calibration DACs, and control logic for calibration and conversion. The DAC consists of an array of 16 capacitors with binary weighted values plus one "dummy LSB" capacitor (Figure 1). During input acquisition in unipolar mode, the array's common terminal is connected to AGND and all free terminals are connected to the input signal (AIN). After acquisition, the common terminal is disconnected from AGND and the free terminals are
disconnected from AIN, trapping a charge proportional to the input voltage on the capacitor array. The free terminal of the MSB (largest) capacitor is connected to the reference (REF), which pulls the common terminal (connected to the comparator) positive. Simultaneously, the free terminals of all other capacitors in the array are connected to AGND, which drives the comparator input negative. If the analog input is near VREF, connecting the MSB's free terminal to REF only pulls the comparator input slightly positive. However, connecting the remaining capacitor's free terminals to ground drives the comparator input well below ground, so the comparator input is negative, the comparator output is low, and the MSB is set high. If the analog input is near ground, the comparator output is high and the MSB is low. Following this, the next largest capacitor is disconnected from AGND and connected to REF, and the comparator determines the next bit. This continues until all bits have been determined. For a bipolar input range, the MSB capacitor is connected to REF rather than AIN during input acquisition, which results in an input range of VREF to -VREF.
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16-Bit, 85ksps ADC with 10A Shutdown MAX195
MSB 32,768C 16,384C 4C 2C
LSB C
DUMMY C
AIN REF AGND
Figure 1. Capacitor DAC Functional Diagram
tCAL
CLK tRCH RESET tRCS
EOC
CALIBRATION BEGINS MAX195 OPERATION HALTS
CALIBRATION ENDS
Figure 2. Initiating Calibration
Calibration
In an ideal DAC, each of the capacitors associated with the data bits would be exactly twice the value of the next smaller capacitor. In practice, this results in a range of values too wide to be realized in an economically feasible size. The capacitor array actually consists of two arrays, which are capacitively coupled to reduce the LSB array's effective value. The capacitors in the MSB array are production trimmed to reduce errors. Small variations in the LSB capacitors contribute insignificant errors to the 16-bit result. Unfortunately, trimming alone does not yield 16-bit performance or compensate for changes in performance due to changes in temperature, supply voltage, and other parameters. For this reason, the MAX195 includes a calibration DAC for each capacitor in the MSB array. These DACs are capacitively coupled to the main DAC
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output and offset the main DAC's output according to the value on their digital inputs. During calibration, the correct digital code to compensate for the error in each MSB capacitor is determined and stored. Thereafter, the stored code is input to the appropriate calibration DAC whenever the corresponding bit in the main DAC is high, compensating for errors in the associated capacitor. The MAX195 calibrates automatically on power-up. To reduce the effects of noise, each calibration experiment is performed many times and the results are averaged. Calibration requires about 14,000 clock cycles, or 8.2ms at the highest clock (CLK) speed (1.7MHz). In addition to the power-up calibration, bringing RESET low halts MAX195 operation, and bringing it high again initiates a calibration (Figure 2).
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16-Bit, 85ksps ADC with 10A Shutdown MAX195
tCC1 tCC2 CLK
tCEL EOC
tCEH
*
CONV tCW TRACK/HOLD
tAQ
CONVERSION ENDS
CONVERSION BEGINS
* THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION
Figure 3. Initiating Conversions--At least 3 CLK cycles since end of previous conversion.
If the power supplies do not settle within the MAX195's power-on delay (500ns minimum), power-up calibration may begin with supply voltages that differ from the final values and the converter may not be properly calibrated. If so, recalibrate the converter (pulse RESET low) before use. For best DC accuracy, calibrate the MAX195 any time there is a significant change in supply voltages, temperature, reference voltage, or clock characteristics (see External Clock section) because these parameters affect the DC offset. If linearity is the only concern, much larger changes in these parameters can be tolerated. Because the calibration data is stored digitally, there is no need either to perform frequent conversions to maintain accuracy or to recalibrate if the MAX195 has been held in shutdown for long periods. However, recalibration is recommended if it is likely that ambient temperature or supply voltages have significantly changed since the previous calibration.
input (AIN = 0V to VREF). Bringing BP/UP/SHDN low places the MAX195 in its 10A shutdown mode. A logic low on RESET halts MAX195 operation. The rising edge of RESET initiates calibration as described in the Calibration section above. Begin a conversion by bringing CONV low. After conversion begins, additional convert start pulses are ignored. The convert signal must be synchronized with CLK. The falling edge of CONV must occur during the period shown in Figures 3 and 4. When CLK is not directly controlled by your processor, two methods of ensuring synchronization are to drive CONV from EOC (continuous conversions) or to gate the conversion-start signal with the conversion clock so that CONV can go low only while CLK is low (Figure 5). Ensure that the maximum propagation delay through the gate is less than 40ns. The MAX195 automatically ensures four CLK periods for track/hold acquisition. If, when CONV is asserted, at least three clock (CLK) cycles have passed since the end of the previous conversion, a conversion will begin on CLK's next falling edge and EOC will go high on the following falling CLK edge (Figure 3). If, when convert is asserted, less than three clock cycles have passed, a conversion will begin on the fourth falling clock edge
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Digital Interface
The digital interface pins consist of BP/UP/SHDN, CLK, SCLK, EOC, CS, CONV, and RESET. BP/UP/SHDN is a three-level input. Leave it floating to configure the MAX195's analog input in bipolar mode (AIN = -VREF to VREF) or connect it high for a unipolar
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16-Bit, 85ksps ADC with 10A Shutdown MAX195
tCC1 tCC2 CLK tCEL EOC tCEH
*
CONV
tCW TRACK/HOLD tAQ
CONVERSION ENDS
CONVERSION BEGINS
* THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION
Figure 4. Initiating Conversions--Less than 3 CLK cycles since end of previous conversion.
after the end of the previous conversion and EOC will go high on the following CLK falling edge (Figure 4).
External Clock The conversion clock (CLK) should have a duty cycle between 25% and 75% at 1.7MHz (the maximum clock frequency). For lower frequency clocks, ensure the minimum high and low times exceed 150ns. The minimum clock rate for accurate conversion is 125Hz for temperatures up to +70C or 1kHz at +125C due to leakage of the sampling capacitor array. In addition, CLK should not remain high longer than 50ms at temperatures up to +70C or 500s at +125C. If CLK is held high longer than this, RESET must be pulsed low to initiate a recalibration because it is possible that state information stored in internal dynamic memory may be lost. The MAX195's clock can be stopped indefinitely if it is held low. If the frequency, duty cycle, or other aspects of the clock signal's shape change, the offset created by coupling between CLK and the analog inputs (AIN and REF) changes. Recalibration corrects for this offset and restores DC accuracy.
SPI/QSPI are trademarks of Motorola Corp.
8
Output Data The conversion result, clocked out MSB first, is available on DOUT only when CS is held low. Otherwise, DOUT is in a high-impedance state. There are two ways to read the data on DOUT. To read the data bits as they are determined (at the CLK clock rate), hold CS low during the conversion. To read results between conversions, hold CS low and clock SCLK at up to 5MHz. If you read the serial data bits as they are determined, EOC frames the data bits (Figure 6). Conversion begins with the first falling CLK edge, after CONV goes low and the input signal has been acquired. Data bits are shifted out of DOUT on subsequent falling CLK edges. Clock data in on CLK's rising edge or, if the clock speed is greater than 1MHz, on the following falling edge of CLK to meet the maximum CLK-to-DOUT timing specification. See the Operating Modes and SPITM/QSPITM Interfaces section for additional information. Reading the serial data during the conversion results in the maximum conversion throughput, because a new conversion can begin immediately after the input acquisition period following the previous conversion.
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16-Bit, 85ksps ADC with 10A Shutdown MAX195
START
MAX195
CONV CLK
START
CLK
CONV SEE DIGITAL INTERFACE SECTION
Figure 5. Gating CONV to Synchronize with CLK
CS
CONV tCW CLK (CASE 1) CLK (CASE 2) tCEH EOC tDV DOUT
B15 FROM PREVIOUS CONVERSION
tCEL
tCD B15 MSB B14 B13 B12 B2 B1 B0 LSB CONVERSION ENDS B15 tDH
CONVERSION BEGINS CASE 1: CLK IDLES LOW, DATA LATCHED ON RISING EDGE (CPOL = 0, CPHA = 0) CASE 2: CLK IDLES LOW, DATA LATCHED ON FALLING EDGE (CPOL = 0, CPHA = 1) NOTE: ARROWS ON CLK TRANSITIONS INDICATE LATCHING EDGE
Figure 6. Output Data Format, Reading Data During Conversion (Mode 1)
If you read the data bits between conversions, you can: 1) count CLK cycles until the end of the conversion, or 2) poll EOC to determine when the conversion is finished, or 3) generate an interrupt on EOC's falling edge.
Note that the MSB conversion result appears at DOUT after CS goes low, but before the first SCLK pulse. Each subsequent SCLK pulse shifts out the next conversion bit. The 15th SCLK pulse shifts out the LSB. Additional clock pulses shift out zeros.
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16-Bit, 85ksps ADC with 10A Shutdown MAX195
EOC CS
tCONV tCSS tCSH
SCLK (CASE 1) SCLK (CASE 2) SCLK (CASE 3)
DOUT tDV
B15 MSB
B14 tSD
B13
B12
B11
B3
B2
B1
B0 LSB tDH
CASE 1: SCLK IDLES LOW, DATA LATCHED ON RISING EDGE (CPOL = 0, CPHA = 0) CASE 2: SCLK IDLES LOW, DATA LATCHED ON FALLING EDGE (CPOL = 0, CPHA = 1) CASE 3: SCLK IDLES HIGH, DATA LATCHED ON FALLING EDGE (CPOL = 1, CPHA = 0) NOTE: ARROWS ON SCLK TRANSITIONS INDICATE LATCHING EDGE
Figure 7. Output Data Format, Reading Data Between Conversions (Mode 2)
+5V -5V 10F 1 2 CONVERSION CLOCK 3 4 5 6 7 8 0.1F BP/UP/ SHDN CLK VDDA VSSA 16 15 14 13 12 11 10 9 REFERENCE (0V TO VDDA) ANALOG INPUT 0.1F 10F
SCLK MAX195 AGND VDDD DOUT DGND EOC CS AIN REF VSSD RESET CONV
Data is clocked out on SCLK's falling edge. Clock data in on SCLK's rising edge or, for clock speeds above 2.5MHz, on the following falling edge to meet the maximum SCLK-to-DOUT timing specification (Figure 7). The maximum SCLK speed is 5MHz. See the Operating Modes and SPI/QSPI Interfaces section for additional information. When the conversion clock is near its maximum (1.7MHz), reading the data after each conversion (during the acquisition time) results in lower throughput (about 70ksps max) than reading the data during conversions, because it takes longer than the minimum input acquisition time (four cycles at 1.7MHz) to clock 16 data bits at 5Mbps. After the data has been clocked in, leave some time (about 1s) for any coupled noise on AIN to settle before beginning the next conversion. Whichever method is chosen for reading the data, conversions can be individually initiated by bringing CONV low, or they can occur continuously by connecting EOC to CONV. Figure 8 shows the MAX195 in its simplest operational configuration.
Figure 8. MAX195 in the Simplest Operating Configuration
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16-Bit, 85ksps ADC with 10A Shutdown MAX195
Table 1. Low-ESR Capacitor Suppliers
COMPANY Sprague AVX Sanyo Nichicon CAPACITOR 595D series, 592D series TPS series OS-CON series, MVGX series PL series FACTORY FAX [COUNTRY CODE] 1-603-224-1430 1-207-283-1941 81-7-2070-1174 1-708-843-2798 USA TELEPHONE 603-224-1961 800-282-4975 619-661-6835 708-843-7500
+5V BRIDGE
INSTRUMENTATION AMPLIFIER
VDDA
AIN
MAX195
REF 47F LOW ESR 0.1F CERAMIC
AGND
Figure 9. Ratiometric Measurement Without an Accurate Reference
__________Applications Information
Reference
The MAX195 reference voltage range is 0V to VDDA. When choosing the reference voltage, the MAX195's equivalent input noise (40V RMS in unipolar mode, 80VRMS in bipolar mode) should be considered. Also, if VREF exceeds VDDA, errors will occur due to the internal protection diodes that will begin to conduct, so use caution when using a reference near VDDA (unless VREF and VDDA are virtually identical). V REF must never exceed its absolute maximum rating (VDDA + 0.3V). The MAX195 needs a good reference to achieve its rated performance. The most important requirement is that the reference must present a low impedance to the REF input. This is often achieved by buffering the reference through an op amp and bypassing the REF input with a large (1F to 47F), low-ESR capacitor in parallel with a 0.1F ceramic capacitor. Low-ESR capacitors are available from the manufacturers listed in Table 1. The reference must drive the main conversion DAC capacitors as well as the capacitors in the calibration
DACs, all of which may be switching between GND and REF at the conversion clock frequency. The total capacitive load presented can exceed 1000pF and, unlike the analog input (AIN), REF is sampled continuously throughout the conversion. The first step in choosing a reference circuit is to decide what kind of performance is required. This often suggests compromises made in the interests of cost and size. It is possible that a system may not require an accurate reference at all. If a system makes a ratiometric measurement such as Figure 9's bridge circuit, any relatively noise-free voltage that presents a low impedance at the REF input will serve as a reference. The +5V analog supply suffices if you use a large, lowimpedance bypass capacitor to keep REF stable during switching of the capacitor arrays. Do not place a resistance between the +5V supply and the bypass capacitor, because it will cause linearity errors due to the dynamic REF input current, which typically ranges from 300A to 400A. Figure 10 shows a more typical scheme that provides good AC accuracy. The MAX874's initial accuracy can
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16-Bit, 85ksps ADC with 10A Shutdown MAX195
+15V +5V 0.1F 0.1F VIN COMP 8 2 7 6 3 0.1F 0.1F -15V 0.1F 10 10 0.1F 1N914 VSSA 15 -5V AGND 14 2 2k 1k 1N914 16 VDDA
MAX874
VOUT GND 4 6
1000pF 4.096V
MAX195
12 REF
MAX427
4 47F LOW ESR
Figure 10. Typical Reference Circuit for AC Accuracy
VIN 8V 2 IN
MAX6241
2.2F
OUT
6
12
MAX195
REF
3
NR GND 4
TRIM
5
10k
2.2F
0.1F AGND 14
1F
Figure 11. High-Accuracy Reference
be improved by trimming, but the drift is too great to provide good stability over temperature. The MAX427 buffer provides the necessary drive current to stabilize the REF input quickly after capacitance changes. The reference inaccuracies contribute additional fullscale error. A reference with less than 1216 total error (15 parts per million) over the operating temperature range is required to limit the additional error to less than 1LSB. The MAX6241 achieves a drift specification
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of 1ppm/C (typ). This allows reasonable temperature changes with less than 1LSB error. While the MAX6241's initial-accuracy specification (0.02%) results in an offset error of about 14LSB, the reference voltage can be trimmed or the offset can be corrected in software if absolute DC accuracy is essential. Figure 11's circuit provides outstanding temperature stability and also provides excellent DC accuracy if the initial error is corrected.
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16-Bit, 85ksps ADC with 10A Shutdown MAX195
+5V
+15V
VDDA
10 AIN INPUT SIGNAL -15V 1N914 DIODE CLAMPS
MAX195
VSSA
-5V
Figure 12. Analog Input Protection for Overvoltage or Improper Supply Sequence
REF and AIN Input Protection
The REF and AIN signals should not exceed the MAX195 supply rails. If this can occur, diode clamp the signal to the supply rails. Use silicon diodes and a 10 current-limiting resistor (Figures 10 and 12) or Schottky diodes without the resistor. When using the current-limiting resistor, place the resistor between the appropriate input (AIN or REF) and any bypass capacitor. While this results in AC transients at the input due to dynamic input currents, the transients settle quickly and do not affect conversion results. Improperly placing the bypass capacitor directly at the input forms an RC lowpass filter with the current-limiting resistor, which averages the dynamic input current and causes linearity errors.
Analog Input
The MAX195 uses a capacitive DAC that provides an inherent track/hold function. The input impedance is typically 30 in series with 250pF in unipolar mode and 50 in series with 125pF in bipolar mode.
Input Range The analog input range can be either unipolar (0V to VREF) or bipolar (-VREF to VREF), depending on the state of the BP/UP/SHDN pin (see Digital Interface section). The reference range is 0V to VDDA. When choosing the reference voltage, the equivalent MAX195 input noise (40VRMS in unipolar mode, 80VRMS in bipolar mode) should be considered.
Input Acquisition and Settling Four conversion-clock periods are allocated for acquiring the input signal. At the highest conversion rate, four clock periods is 2.4s. If more than three clock cycles have occurred since the end of the previous conversion, conversion begins on the next falling clock edge after CONV goes low. Otherwise, bringing CONV low begins a conversion on the fourth falling clock edge after the previous conversion. This scheme ensures the minimum input acquisition time is four clock periods. Most applications require an input buffer amplifier. If the input signal is multiplexed, the input channel should be switched near the beginning of a conversion, rather than near the end of or after a conversion (Figure 13). This allows time for the input buffer amplifier to respond to a large step change in input signal. The input amplifier must have a high enough slew rate to complete the required output voltage change before the beginning of the acquisition time. At the beginning of acquisition, the capacitive DAC is connected to the amplifier output, causing some output disturbance. Ensure that the sampled voltage has settled to within the required limits before the end of the acquisition time. If the frequency of interest is low, AIN can be bypassed with a large enough capacitor to charge the capacitive DAC with very little change in voltage (Figure 14). However, for AC use, AIN must be driven by a wideband buffer (at least 10MHz), which must be stable with the DAC's capacitive load (in parallel with any AIN bypass capacitor used) and also must settle quickly (Figure 15 or 16).
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13
16-Bit, 85ksps ADC with 10A Shutdown MAX195
IN1 IN2
A0
A1
4-TO-1 MUX
AIN OUT EOC
MAX195
IN3 IN4
CLK CONVERSION ACQUISITION
EOC
A0
A1
CHANGE MUX INPUT HERE
Figure 13. Change multiplexer input near beginning of conversion to allow time for slewing and settling.
1k +15V +5V
0.1F 2 7 6 IN 3 MAX400 4 0.1F -15V
1000pF
1N914 10 AIN
100 1N914 1.0F -5V
Figure 14. MAX400 Drives AIN for Low-Frequency Use
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16-Bit, 85ksps ADC with 10A Shutdown
Digital Noise Digital noise can easily be coupled to AIN and REF. The conversion clock (CLK) and other digital signals that are active during input acquisition contribute noise to the conversion result. If the noise signal is synchronous to the sampling interval, an effective input offset is produced. Asynchronous signals produce random noise on the input, whose high-frequency components may be aliased into the frequency band of interest. Minimize noise by presenting a low impedance (at the frequencies contained in the noise signal) at the inputs. This requires bypassing AIN to AGND, or buffering the input with an amplifier that has a small-signal bandwidth of several megahertz, or preferably both. AIN has a bandwidth of about 16MHz. Offsets resulting from synchronous noise (such as the conversion clock) are canceled by the MAX195's calibration scheme. However, because the magnitude of the offset produced by a synchronous signal depends on the signal's shape, recalibration may be appropriate if the shape or relative timing of the clock or other digital signals change, as might occur if more than one clock signal or frequency is used. Distortion Avoid degrading dynamic performance by choosing an amplifier with distortion much less than the MAX195's THD (-97dB, or 0.0014%) at frequencies of interest. If the chosen amplifier has insufficient common-mode rejection, which results in degraded THD performance, use the inverting configuration (positive input grounded) to eliminate errors from this source. Low temperature-coefficient, gain-setting resistors reduce linearity errors caused by resistance changes due to self-heating. Also, to reduce linearity errors due to finite amplifier gain, use an amplifier circuit with sufficient loop gain at the frequencies of interest (Figures 14, 15, 16).
MAX195
DC Accuracy If DC accuracy is important, choose a buffer with an offset much less than the MAX195's maximum offset (3LSB = 366V for a 4V input range), or whose offset can be trimmed while maintaining good stability over the required temperature range. Recommended Circuits Figure 14 shows a good circuit for DC and low-frequency use. The MAX400 has very low offset (10V) and drift (0.2V/C), and low voltage noise (10nV/Hz) as well. However, its gain-bandwidth product (GBW) is much too low to drive AIN directly, so the analog input is bypassed to present a low impedance at high frequencies. The large bypass capacitor is isolated from the amplifier output by a 100 resistor, which provides additional noise filtering. Since the 15V supplies exceed the AIN range, add protection diodes at AIN (see REF and AIN Input Protection section). Figure 15 shows a wide-bandwidth amplifier (MAX427) driving a wideband video buffer, which is capable of driving AIN and a small bypass capacitor (for noise reduction) directly. The video buffer is inside the MAX427's feedback loop, providing good DC accuracy, while the buffer's low output impedance and highcurrent capability provide good AC performance. AIN is diode-clamped to the 5V rails to prevent overvoltage. The MAX427's 15V maximum offset voltage, 0.8V/C maximum drift, and less than 5nV/Hz noise specifications make this an excellent choice for AC/DC use.
1k +15V 100pF 1 6 IN 3 MAX427 4 0.1F -15V -15V 1k 2 +15V +5V
0.1F 2 7
0.1F
1N914 10 AIN 1N914
ELANTEC EL2003
4
7
0.0033F 0.1F -5V
Figure 15. AIN Buffer for AC/DC Use
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16-Bit, 85ksps ADC with 10A Shutdown
If 15V supplies are unavailable, Figure 16's circuit works very well with the 5V analog supplies used by the MAX195. The MAX410 has a minimum 3.5V common-mode input range, with a similar output voltage swing, which allows use of a reference voltage up to 3.5V. The offset voltage (250V) is about 2LSB. The drift (1V/C), unity-gain bandwidth (28MHz), and low voltage noise (2.4nV/Hz) are appropriate for 16-bit performance.
MAX195
Operating Modes and SPI/QSPI Interfaces
The two basic interface modes are defined according to whether serial data is received during the conversion (clocked with CLK, SCLK unused) or in bursts between conversions (clocked with SCLK). Each mode is presented interfaced to a QSPI processor, but is also compatible with SPI.
510 +5V 0.1F 2 7 6 IN 3 MAX410 4 0.1F -5V 0.01F 22 AIN
Figure 16. 5V Buffer for AC/DC Use Has 3.5V Swing
QSPI
PCS0
CS CONV
SCK MISO
CLK MAX195 DOUT SCLK
GPT
*OC3 *IC1 *OC2
BP/UP/SHDN EOC RESET
Mode 1 (Simultaneous Conversion and Data Transfer) In this mode, each data bit is read from the MAX195 during the conversion as it is determined. SCLK is grounded and CLK is used as both the conversion clock and the serial data clock. Figure 17 shows a QSPI processor connected to the MAX195 for use in this mode and Figure 18 is the associated timing diagram. In addition to the standard QSPI interface signals, general I/O lines are used to monitor EOC and to drive BP/UP/SHDN and RESET. The two general output pins may not be necessary for a given application and, if I/O lines are unavailable, the EOC connection can be omitted as well. The EOC signal is monitored during calibration to determine when calibration is finished and before beginning a conversion to ensure the MAX195 is not in mid-conversion, but it is possible for a system to ignore EOC completely. On power-up or after pulsing RESET low, the P must provide 14,000 CLK cycles to complete the calibration sequence (Figure 2). One way to do this is to toggle CLK and monitor EOC until it goes low, but it is possible to simply count 14,000 CLK cycles to complete the calibration. Similarly, it is unnecessary to check the status of EOC before beginning a conversion if you are sure the last conversion is complete. This can be done by ensuring that every conversion consists of at least 20 CLK cycles. Data is clocked out of the MAX195 on CLK's falling edge and can be clocked into the P on the rising edge or the following falling edge. If you clock data in on the rising edge (SPI/QSPI with CPOL = 0 and CPHA = 0; standard MicroWireTM: Hitachi H8), the maximum CLK rate is given by:
1 fCLK(max) = 1/ 2 t CD + t SD where tCD is the MAX195's CLK-to-DOUT valid delay and tSD is the data setup time for your P.
* THE USE OF THESE SIGNALS ADDS FLEXIBILITY AND FUNCTIONALITY BUT IS NOT REQUIRED TO IMPLEMENT THE INTERFACE.
Figure 17. MAX195 Connection to QSPI Processor Clocking Data Out During Conversions
16
MicroWire is a trademark of National Semiconductor Corp.
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16-Bit, 85ksps ADC with 10A Shutdown MAX195
CS, CONV
CLK
EOC
DOUT tDV DATA LATCHED:
B15 FROM PREVIOUS CONVERSION
B15 tCD
B14
B2
B1
B0
B15 tDH
Figure 18. Timing Diagram for Circuit of Figure 17 (Mode 1)
QSPI
PCS0 SCK MISO CS SCLK DOUT BP/UP/SHDN EOC RESET CONV IC3 74HC32 1.7MHz 1.3s START CLK
If clocking data in on the falling edge (CPOL = 0, CPHA = 1), the maximum CLK rate is given by: 1 fCLK(max) = t CD + t SD Do not exceed the maximum CLK frequency given in the Electrical Characteristics table. To clock data in on the falling edge, your processor hold time must not exceed tCD minimum (100ns). While QSPI can provide the required 20 CLK cycles as two continuous 10-bit transfers, SPI is limited to 8-bit transfers. This means that with SPI, a conversion must consist of three 8-bit transfers. Ensure that the pauses between 8-bit operations at your selected clock rate are short enough to maintain a 20ms or shorter conversion time, or the leakage of the capacitive DAC may cause errors. Complete source code for the Motorola 68HC16 and the MAX195 evaluation kit (EV kit) using this mode is available with the MAX195 EV kit.
MAX195
GPT
OC3 IC1 OC2
Figure 19. MAX195 Connection to QSPI Processor Clocking Data Out with SCLK Between Conversions
Mode 2 (Asynchronous Data Transfer) This mode uses a conversion clock (CLK) and a serial clock (SCLK). The serial data is clocked out between conversions, which reduces the maximum throughput for high CLK rates, but may be more convenient for some applications. Figure 19 is a block diagram with a QSPI processor (Motorola 68HC16) connected to the MAX195. Figure 20 shows the associated timing diagram. Figure 21 gives an assembly language listing for this arrangement.
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16-Bit, 85ksps ADC with 10A Shutdown MAX195
588ns CLK
START
EOC
CS 239ns SCLK 4.19MHz
DOUT 1.3s * INTERRUPT LATENCY OF THE PROCESSOR CONVERSION TIME 9.4s 17s*
B15
B14 B13 5.1s
B3 B2
B1
B0 4s
Figure 20. Timing Diagram for Circuit of Figure 19 (Mode 2)
An OR gate is used to synchronize the "start" signal to the asynchronous CLK, as described in the External Clock section. As with Mode 1, the QSPI processor must run CLK during calibration and either count CLK cycles or, as is done here, monitor EOC to determine when calibration is complete. Also, EOC is polled by the P to determine when a conversion result is available. When EOC goes low, data is clocked out at the highest QSPI data rate (4.19Mbps). After the data is transferred, a new conversion can be initiated whenever desired. The timing specification for SCLK-to-DOUT valid (tSD) imposes some constraints on the serial interface. At SCLK rates up to 2.5Mbps, data is clocked out of the MAX195 by a falling edge of SCLK and may be clocked into the P by the next rising edge (CPOL = 0, CPHA = 0). For data rates greater than 2.5Mbps (or for lower rates, if desired) it is necessary to clock data out of the MAX195 on SCLK's falling edge and to clock it into the P on SCLK's next falling edge (CPOL = 0, CPHA = 1). Also, your processor hold time must not exceed tSD minimum (20ns). As with CLK in mode 1, maximum SCLK rates may not be possible with some interface specifications that are subsets of SPI.
Supplies, Layout, Grounding and Bypassing
For best system performance, use printed circuit boards with separate analog and digital ground planes. Wire-wrap boards are not recommended. The two ground planes should be tied together at the lowimpedance power-supply source and at the MAX195 (Figure 22.) If the analog and digital supplies come from the same source, isolate the digital supply from the analog supply with a low-value resistor (10). Constraints on sequencing the four power supplies are as follows. * Apply VDDA before VDDD. * Apply VSSA before VSSD. * Apply AIN and REF after VDDA and VSSA are present. * The power supplies should settle within the MAX195's power-on delay (minimum 500ns) or you should recalibrate the converter (pulse RESET low) before use.
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16-Bit, 85ksps ADC with 10A Shutdown MAX195
Figure 21. MAX195 Code Listing for 68HC16 Module and Circuit of Figure 19
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16-Bit, 85ksps ADC with 10A Shutdown MAX195
Figure 21. MAX195 Code Listing for 68HC16 Module and Circuit of Figure 19 (continued)
20 ______________________________________________________________________________________
16-Bit, 85ksps ADC with 10A Shutdown MAX195
Figure 21. MAX195 Code Listing for 68HC16 Module and Circuit of Figure 19 (continued)
Be sure that digital return currents do not pass through the analog ground and that return-current paths are low impedance. A 5mA current flowing through a PC board ground trace impedance of only 0.05 creates an error voltage of about 250V, or about 2LSBs error with a 4V full-scale system. The board layout should ensure as much as possible that digital and analog signal lines are kept separate. Do not run analog and digital (especially clock) lines parallel to one another. If you must cross one with the other, do so at right angles. The ADC's high-speed comparator is sensitive to highfrequency noise on the VDDA and VSSA power supplies. Bypass these supplies to the analog ground plane with 0.1F in parallel with 1F or 10F low-ESR capacitors. Keep capacitor leads short for best supplynoise rejection.
Shutdown
The MAX195 may be shut down by pulling BP/UP/ SHDN low. In addition to lowering power dissipation to 10W (100W max) when the device is not in use, you can save considerable power by shutting the converter down for short periods between conversions. There is no need to perform a reset (calibration) after the converter has been shut down unless the time in shutdown
is long enough that the supply voltages or ambient temperature may have changed. The time required for the converter to "wake up" and settle depends heavily on the amount of additional error acceptable. For 0.5LSB additional error, 3.2s is sufficient settling time and also allows enough time for reacquisition of the analog input signal. 50s settling is required for less than 0.1LSB error. Figure 23 is a graph of theoretical power consumption vs. conversions per second for the MAX195 that assumes the conversion clock is 1.7MHz and the converter is shut down as much as possible between conversions. Stop CLK before shutting down the MAX195. CLK must be stopped without generating short clock pulses. Short CLK pulses (less than 150ns), or shutting down the MAX195 without stopping CLK, may adversely affect the MAX195's internal calibration data. In applications where CLK is free-running and asynchronous, use the circuit of Figure 24 to stop CLK cleanly. To minimize the time required to settle and perform a conversion, shut the converter down only after a conversion is finished and the desired mode (unipolar or bipolar) has been set. This ensures that the sampling capacitor array is properly connected to the input signal. If shut down in mid-conversion, when awakened,
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16-Bit, 85ksps ADC with 10A Shutdown MAX195
10 VDDD 10F 5V 10F 0.1F DGND AGND 10F 5V 10F 0.1F VSSA VSSD 10 0.01 1 10 100 1000 10,000 100,000 CONVERSIONS PER SECOND 0.1F 0.1F VDDA POWER DISSIPATION (mW) 10 20s WAKE-UP DELAY 0.25LSB ERROR 1 50s WAKE-UP DELAY 0.01LSB ERROR
MAX195-FIG23
100
MAX195
0.1 3.2s WAKE-UP DELAY 0.5LSB ERROR
Figure 22. Supply Bypassing and Grounding
Figure 23. Power Dissipation vs. Conversions/sec When Shutting the MAX195 Down Between Conversions
the MAX195 finishes the old conversion, allows four clock (CLK) cycles for input acquisition, then begins the new conversion.
_____________Dynamic Performance
High-speed sampling capability, 85ksps throughput, and wide dynamic range make the MAX195 ideal for AC applications and signal processing. To support these and other related applications, Fast Fourier Transform (FFT) test techniques are used to guarantee the ADC's dynamic frequency response, distortion, and noise at the rated throughput. Specifically, this involves applying a low-distortion sine wave to the ADC input and recording the digital conversion results for a specified time. The data is then analyzed using an FFT algorithm, which determines its spectral content. Conversion errors are then seen as spectral elements other than the fundamental input frequency.
The theoretical minimum ADC noise is caused by quantization error and is a direct result of the ADC's resolution: SNR = (6.02N + 1.76)dB, where N is the number of bits of resolution. A perfect 16-bit ADC can, therefore, do no better than 98dB. An FFT plot of the output shows the output level in various spectral bands. Figure 25 shows the result of sampling a pure 1kHz sinusoid at 85ksps with the MAX195. By transposing the equation that converts resolution to SNR, we can, from the measured SNR, determine the effective resolution or the "effective number of bits" the ADC provides: N = (SNR - 1.76) / 6.02. Substituting SINAD for SNR in this formula results in a better measure of the ADC's usefulness. Figure 26 shows the effective number of bits as a function of the MAX195's input frequency calculated from the SINAD. If your intended sample rate is much lower than the MAX195's maximum of 85ksps, you can improve your noise performance by taking more samples than necessary (oversampling) and averaging them in software. Figure 27 is a histogram showing 16,384 samples for the MAX195 without averaging, with an ideal "noiseless conversion," and with a running average of five samples. The standard deviation is 0.621LSB without averaging and 0.382LSB with the running average. If fewer data points are needed, normal averaging (e.g., five data points averaged to produce one data point) can be used instead of a running average, with similar results.
Signal-to-Noise Ratio and Effective Number of Bits
Signal-to-Noise Ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other ADC output signals. The output band is limited to frequencies above DC and below one-half the ADC sample rate. This usually (but not always) includes distortion as well as noise components. For this reason, the ratio is sometimes referred to as Signal-to-Noise + Distortion (SINAD).
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16-Bit, 85ksps ADC with 10A Shutdown MAX195
1/2 74HC73 CLOCK SHUTDOWN +5V 2 x CLK J Q K BP/UP/SHDN CK CLK
MAX195
CK (2 x CLK) Q (CLK) J (CLOCK SHUTDOWN)
Figure 24. Circuit to Stop Free-Running Asynchronous CLK
-10 SIGNAL AMPLITUDE (dB) -30 -50 -70 -90 -110 -130 -150 0 5 10 15 20 25 30 35 40 FREQUENCY (kHz) fIN = 1kHz fS = 85kHz TA = +25C
Figure 25. MAX195 FFT Plot
Even better than oversampling and averaging is oversampling and digital filtering. Averaging is just a rough (but computationally simple) type of digital filter. Finite impulse response (and other) digital filter algorithms are readily available, and are useful even with slow processors if the data rate is low or the data does not need to be processed in real-time. When using averaging, be sure to average an odd number of samples to avoid small offset errors caused by asymmetrical rounding. Whether simple averaging or more complex digital filtering is used, the effect of oversampling is to spread the noise across a wider bandwidth. Digital filtering or averaging then eliminates the portion of this noise that lies above the filter's passband, leaving less noise in the passband than if oversampling was not used. An additional benefit of oversampling is that it simplifies the design or choice of an anti-aliasing pre-filter for the input. You can use a filter with a more gradual rolloff, because the sample rate is much higher than the frequency of interest.
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23
16-Bit, 85ksps ADC with 10A Shutdown MAX195
MAX195-26
15 EFFECTIVE BITS 14 13 12 11 10 0.1
fS = 85kHz TA = +25C
95 90 SINAD (dB) 85 80 75 70 65 60
fS = 85kHz TA = +25C
1
10
100
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 26. Effective Bits vs. Input Frequency
Figure 28. Signal-to-Noise + Distortion vs. Frequency
OCCURRENCES OF OUTPUT CODE (THOUSANDS)
This is expressed as follows:
MAX195 FG27
18 16 14 12 10 8 6 4 2 0 8021 8022 8023 8024 8025 8026 8027 OUTPUT CODE (HEXADECIMAL) NO AVERAGING RUNNING AVERAGE OF 5 SAMPLES IDEAL CONVERSION VREF = +4.5V VAIN = +2.25V UNIPOLAR MODE 85ksps
THD = 20log
V22 + V32 + V4 2 + ...+ V 2 N V1
Figure 27. Histogram of 16,384 Conversions Shows Effects of Noise and Averaging
where V1 is the fundamental RMS amplitude, and V 2 through VN are the amplitudes of the 2nd through Nth harmonics. The THD specification in the Electrical Characteristics includes the 2nd through 5th harmonics. In the MAX195, this distortion is caused primarily by the changes in on-resistance of the AIN sampling switches with changing input voltage. These resistance changes, together with the DAC's capacitance (which can also vary with input voltage), cause a varying time delay for AC signals, which causes significant distortion at moderately high frequencies (Figure 28).
Spurious-Free Dynamic Range
Spurious-free dynamic range is the ratio of the fundamental RMS amplitude to the amplitude of the next largest spectral component (in the frequency band above DC and below one-half the sample rate). Usually, this peak occurs at some harmonic of the input frequency. However, if the ADC is exceptionally linear, it may occur only at a random peak in the ADC's noise floor.
Total Harmonic Distortion
If a pure sine wave is input to an ADC, AC integral nonlinearity (INL) of an ADC's transfer function results in harmonics of the input frequency being present in the sampled output data. Total Harmonic Distortion (THD) is the ratio of the RMS sum of all the harmonics (in the frequency band above DC and below one-half the sample rate, but not including the DC component) to the RMS amplitude of the fundamental frequency.
Transfer Function
Figures 29 and 30 show the MAX195's transfer functions. In unipolar mode, the output data is in binary format and in bipolar mode it is offset binary.
24
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MAX195-28
16
100
16-Bit, 85ksps ADC with 10A Shutdown
___________________Chip Topography
11 . . . 111 11 . . . 110 11 . . . 101 11 . . . 100 11 . . . 011 11 . . . 010 00 . . . 110 00 . . . 101 00 . . . 100 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 0V VREF - (1LSB)
MAX195
BP/UP/SHDN CLK SCLK
VSSA VDDA AGND
AIN REF 0.273" (6.93mm)
VDDD
Figure 29. MAX195 Unipolar Transfer Function
DOUT
11 . . . 111 11 . . . 110 11 . . . 101
DGND EOC CONV RESET 0.144" (3.66mm)
VSSD
10 . . . 010 10 . . . 001 10 . . . 000 01 . . . 111 01 . . . 110 00 . . . 010 00 . . . 001 00 . . . 000 -VREF 0V VREF - (1LSB)
CS
TRANSISTOR COUNT: 7966 SUBSTRATE CONNECTED TO VDDA
Figure 30. MAX195 Bipolar Transfer Function
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16-Bit, 85ksps ADC with 10A Shutdown MAX195
________________________________________________________Package Information
PDIPN.EPS
26
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16-Bit, 85ksps ADC with 10A Shutdown
___________________________________________Package Information (continued)
SOICW.EPS
MAX195
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16-Bit, 85ksps ADC with 10A Shutdown MAX195
___________________________________________Package Information (continued)
SBN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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